This invention relates in general to pulsed current sources and more particularly to a circuit that maintains the magnitude of the dc component of the current pulses. In a number of applications in which a pulsed current source is utilized, it is important to preserve the magnitude of the dc component of the current pulses. A particular source of error in the dc component is caused by variations in the duty cycle of the pulses.
An example of a device in which maintenance of the magnitude of the dc component is important is shown in FIG. 3 and is discussed in detail in copending patent application by Thomas Hornak and Gary L. Baldwin entitled "A Binary Scaled Current Array Source For Digital to Analog Converters". FIG. 3 is a block diagram of a binary scaled current source which produces a set of n dc currents I.sub.1, . . . ,I.sub.n. Such a current source is useful in a digital to analog converter which, in response to an n bit binary number, directs selected ones of the I.sub.k to the output of the digital to analog converter to produce an output current proportional to the binary number. In particular, the kth bit is directed to the output if and only if the kth least significant bit of the binary number is a one.
In FIG. 3, a current source 31 produces a dc current I that is switched by a pair of switches M.sub.C0 and M.sub.C1 such as transistors 32 and 33. Switch 32 is responsive to a clock signal CLK and switch 33 is responsive to the complement -CLK of the clock signal so that the current I is conducted through switch 32 to rail 34 only when CLK is high. In effect, dc current source 31 and switches 32-33 function as a pulsed current source 35. A set of control signals B.sub.0, . . . ,B.sub.n control a set of switches M.sub.0, . . . ,M.sub.n in an upper stage 37 of the binary scaled current source such that the dc currents I.sub.1, . . . ,I.sub.n generated by low pass filters LPF are related by I.sub.k =2.sup.k-1 *I.sub.1. Unfortunately, the absolute value of these dc currents can vary if the duty cycle of CLK varies. The effect of this on the digital to analog converter would be that the scale of the output current would not be accurately known.
In accordance with the illustrated preferred embodiment of the present invention shown in FIG. 2, the dc component of the current through switch 14 and currents I.sub.n+1, . . . ,I.sub.n+m are not dumped to ground as is done in FIG. 3 for currents i.sub.0 and I.sub.C1, but instead are supplied through a floating power supply that is a.c. bypassed to ground back to input A of switches M.sub.C0 and M.sub.C1. In effect, the d.c. component of the current through switch M.sub.C1 flows around a first loop that passes through node A. Similarly, the currents I.sub.n+1, . . . ,I.sub.n+m also flow around a second loop that passes through node A. Therefore, all of the current I from source 22 must pass through switches M.sub.1, . . . ,M.sub.n and therefore the sum of the currents I.sub.1, . . . ,I.sub.n is I, regardless of the duty cycle of CLK. The effect of this is that the magnitudes of the currents I.sub.k (for k=1 to n) are unaffected by variations in the duty cycle of CLK.